1. Field of the Invention
The present invention relates generally to a memory system, and more specifically, to an interface and protocol for a memory system that is independent of the memory type utilized.
2. Discussion of the Related Art
Advances in process technology together with trends in system architecture are motivating designers to consider the integration of memory controller functions within the processor. This integration can result in lower costs because of the reduced device count and improved performance due to tighter coupling between the memory controller and the processor. Furthermore, this integration supports the trend away from system architectures with multi-drop buses. Alternate architectures are being considered because the bandwidth of xe2x80x9cfront-side bus plus chipsetxe2x80x9d architectures is limited by long stub lengths and package pin-count constraints. This is a particularly important issue for multiprocessor systems because of the larger number of devices that must share a common bus. The consequence is that multiprocessor systems are moving from shared-memory to distributed-memory architectures. The integration of the memory controller is synergetic with this distributed memory approach.
However, there are a number of issues with directly connecting a memory to a processor. First, support for a particular type or types of memory must be designed into the processor. This approach exposes the processor to market dynamics of the supported memory types and adds risk in terms of market acceptance and market share. For example, the xe2x80x9cbestxe2x80x9d memory type may change between the design start and the product launch. Also, the processor may not be compatible with the input/output voltages of the memory devices. Memory devices typically have higher voltages due to (1) process differences, (2) the high-load multi-drop nature of the memory interconnect, and (3) established standards for memory device input/output voltages. Thirdly, memory expansion is limited to that available on the memory interconnect. For many market segments, limited expansion capability is not acceptable.
Adding an external component to bridge between the processor and the memory devices can revolve the issues involving input/output voltages and memory expansion, but issues involving different types of memory support having to be designed into the processor remain unresolved. If the memory control functions on the processor device and/or the interconnect to the external device have memory dependent functions (i.e., these functions are specific to a particular type of memory device and not compatible with other memory types), then this approach has the same risks mentioned above. There are also other issues with using memory dependent functions, such as that a memory dependent protocol must be developed for communication with the external device. This protocol must comprehend the details of all the memory types to be supported, and so market risks are still present. If a memory type is added later, it requires changes to both the primary and external devices, and may require changes to the protocol as well. This approach results in considerable scheduling difficulties. Therefore, integrating memory dependent functions on a primary device may have a number of undesirable consequences.